1. Field of the Invention
The present invention related to a method for fabricating flip chip ball grid array package structure, and more particularly to a method for detecting the under fill void in the flip chip ball grid array package structure.
2. Description of the Prior Art
Ball grid array (BGA) is an advanced type of integrated circuit packaging technology which is characterized by the use of an organic substrate whose upper surface is mounted with a semiconductor chip and whose lower surface is mounted with a grid array of solder balls. During a surface mount technology process, for example, the BGA package can be mechanically bonded and electrically coupled to a printed circuit board (PCB) by means of these solder balls.
Flip chip ball grid array is a more advanced type of BGA technology that uses flip chip technology in mounting the active side of the chip in an upside-down manner over the substrate and bonded to the same by means of a plurality of solder bumps attached to input/output pads thereon. Due to the inherent coefficient of thermal expansion (CTE) mismatches between the FCBGA package components such as for example the chip, substrate, and underfill (an adhesive flowed between the chip and substrate), high package warpage and thermal stresses are frequently induced in the FCBGA package. These high thermal stresses and warpage not only lead to the delamination in the low-k interconnect layer(s) in the chip, but also cause solder bump cracks leading to failure, degrading the long term operating reliability of the FCBGA package. Furthermore, the substrate onto which the flip chip may be mounted can be a single layer structure, or the substrate may comprise two or many more layers of materials. Often these materials tend to be quite diverse in their composition and structure. The coefficient of thermal expansion for these different layers may be considerably different and may result in uncontrolled bending or thermal induced substrate surface distortions. Such distortions can cause failure of the flip chip or other components of the substrate.
With the introduction of new components and materials such as inorganic substrates (e.g. ceramic) for FCBGA packaging, the above problems become more pronounced due to the coefficient of thermal expansion mismatches among these components.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved FCBGA package that reduces and/or eliminates the component and/or board level reliability problems of conventional FCBGA packages due the coefficient of thermal expansion mismatches among these components.
In addition, FIG. 1A shows a high-performance and enhanced flip chip ball grid array package structure with a metal ring that is to be supported the heat plate whose covers on the flip chip ball array package structure. In FIG. 1A, the conventional flip chip ball grid array package structure includes a substrate 100, a chip 110 which is mounted on the top surface (not shown) of the substrate 100, a metal ring 130 which is disposed around the peripheral of the top surface of the chip 110, and a heat plate 140 which is disposed on the top of the metal ring 130. Generally, the chip 110 is electrically connected the substrate 100 by solder ball 112 which is covered by the under fill material 114. The plurality of solder balls 150 is disposed on the back surface (not shown) of the substrate 100, so that the package structure can be electrically connected with the exterior electronic device.
The above package structure must be required a lot of processes with high temperature when the packaging process is performed, for example, the package structure is disposed in an environment with high temperature during the reflow process or under fill process. Nevertheless, when the substrate 100 is disposed under the environment with high temperature, the substrate could be overheated to generate the warpage. Now, the metal ring 130 can increase the strength for the substrate 100 to avoid the excessive warpage generating in the substrate 100.
Because of the metal ring 130 is merely disposed on the top surface of the substrate 100 for the conventional package structure, the metal ring 130 would be peeled when the excessive deflection is generated in the substrate 100.
Beside, the inadequate height of the solder ball 112 on the active surface of the chip 110 will introduce the void 120 (as shown in FIG. 1B) that is formed in the connecting interface between the molding material 114 and the solder ball 112 on the active surface of the chip 110 when the molding material 114 is filled to encapsulate the chip 110 and the substrate 100. Thus, the circuit short for the connecting elements of the chip 110 would be generated, and the package chip or package structure could not be operated.